The present invention relates to integrated circuit development, and more specifically, to the identification of hotspots in congestion analysis during the physical design of the integrated circuit.
The development of an integrated circuit (i.e., chip) involves several phases such as the logic design phase, the physical design phase, and the fabrication (i.e., manufacturing) phase. Many of the phases or processes that are part of the phases can be performed iteratively. During the physical design phase, placement of the components and routing of the wires that interconnect components is determined. As the density of components and the number of metal layers increases, the routing process becomes more challenging. Specifically, routing wires to avoid congested areas becomes more difficult. The management of congestion is necessary for both performance and cost. For example, high congestion can require an increased die size or more metal layers. Further, long wire routes resulting from congestion can increase noise and create new critical paths that affect signal integrity and timing. A congestion map can indicate areas with relatively higher densities of components and wires. However, areas of congestion can change based on placement, buffering, and layer assignment over iterations of the physical design. In addition, the relative arrangement of areas of high congestion can affect routing.